(1) Field of the Invention
The present invention relates to a bus communication device that performs transfer of data between masters via a shared memory.
(2) Description of the Related Art
Bus communication between a plurality of masters with use of a shared memory is performed conventionally. In such bus communication, upon completing access to the shared memory, a communication origin master (hereinafter referred to simply as an origin master) outputs a trigger such as an interrupt or a completion notification signal to a communication destination master (hereinafter referred to simply as a destination master). The destination master is activated by the trigger from the origin master, and proceeds to a phase for generating a memory access command for accessing the shared memory.
Taking the bus communication apparatus of Patent Document 1 as one example, in a data transfer between processors, a transfer origin processor writes data to a shared memory, and when the writing is complete, outputs an interrupt to a transfer destination processor. Having received the interrupt, the transfer destination processor accesses the shared memory, and reads the data that has been written to the shared memory.
According to the technique disclosed in Patent Document 2, in the transfer of data from a local memory in a transfer origin system to a transfer destination system via a shared memory, data in the local memory in the transfer origin system is written directly to the shared memory using a direct memory access controller. When the writing is complete, the direct memory access controller issues an interrupt to the transfer destination system informing that the writing is complete, via an interrupt branch circuit. Having received the interrupt, the transfer destination system accesses the shared memory, and reads the data that has been written to the shared memory.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-86615
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2004-70642
In a conventional bus communication apparatus such as those described above, the destination master is triggered to move to the memory access command generation phase by an interrupt, a origin completion notification signal, or the like, issued due to the origin master completing a data transfer that involves accessing a memory.
This, however, gives rise the problem that despite there being cases in which data coherency would be maintained even if the destination master issued a command in advance of the origin master completing the data transfer, the destination master is unable to issue the command in advance.